Pixel matrix with compensation of ohmic drops on the power supplies

ABSTRACT

A matrix microelectronic device includes elementary cells laid out according to a matrix. Each cell has a current source formed by a current source transistor. A source electrode of the transistor is connected to a source biasing conductor line of a plurality of source biasing conductor lines. A gate electrode of the transistor is connected to a gate biasing conductor line of a plurality of gate biasing conductor lines. A biasing device biases the gate biasing conductor lines and includes at least one first connection line that is connected to at least several of the gate biasing conductor lines. The biasing device includes a voltage generator or a current generator that causes a variation of potentials along the first connection line, thereby compensating a corresponding variation of potentials along the source biasing conductor lines. The device can include an addressing circuit for addressing horizontal lines or rows of the matrix.

TECHNICAL FIELD

The invention relates to the field of microelectronic devices formed byelementary cells or matrix pixels and especially applies to largematrices that have a current source in each pixel, for example X-raydetector matrices.

The invention permits homogeneous consumption and performances to beobtained between the pixels or elementary cells of a matrix device inwhich the cells are respectively equipped with a current source.

The invention provides for the use of a matrix microelectronic deviceformed by elementary cells respectively comprising a current sourcewhose consumption depends on a difference of two biasing potentials, andmeans for compensating an ohmic drop in one or several lines carryingone of said two potentials to the pixels.

STATE OF THE PRIOR ART

In a matrix microelectronic device, such as an X-ray detector matrix,the signals sent from the elementary cells or pixels of the matrix aregenerally read by scanning the horizontal lines or rows of the matrix. Aselection of a given line or given horizontal row of the matrix may forexample permit the output signals from the pixels of this given line tobe obtained on the vertical columns or rows of the matrix.

The power supply or pilot voltages are supplied to the pixels, by meansof a conductive network that may be for example in the form ofconductive lines, or conductive gates. The power supply or pilotvoltages undergo ohmic drops in this conductive network, which may, onlarge matrices, reach several tens of millivolts or even more.

An example of an X-ray detection matrix microelectronic device, formedby a 2*2 matrix, of 2 horizontal rows and 2 vertical rows of elementarycells also called pixels 10 ₁₁, 10 ₁₂, 10 ₂₁, 10 ₂₂, is illustrated inFIG. 1. In this device, the consumption of each pixel is mainly that ofa current source formed by a transistor T₁. This current source is onlyactivated when a horizontal row or line of the matrix is selected. Thecurrent supplied by this current source depends on the voltageVgs=(Vg−Vs) of this transistor T₁.

In the case of the current source transistor T₁ being biased in lowinversion, its current Ids between drain and source may be defined bythe following relationship: Ids=(I₀*e^((Vgs/(kT/q)))

where:

I₀: a constant which especially depends on the geometry of thetransistor T,

K: the Boltzmann constant,

T: the temperature in Kelvin's,

q: the charge.

This relation shows that the current Ids is likely to vary very quickly,for example by a factor of 2 for a relatively low variation of thevoltage gate-source Vgs, of around 18 mV, at ambient temperature.

In a case where the transistor T₁ is biased with high inversion, theequation defining the current Ids is different, but the problem is thesame. The application of the potential Vg to the gate of the transistorT₁, causes very little consumption of current at the gate. Consequently,in a conductive network supplying the potential Vg to all of the gatesof the transistor T₁ acting as current sources, the ohmic drop isrelatively low. In return, the application of the potential Vs to thesource of the transistor T₁ causes greater consumption of current at thesource. The corresponding conductive network designed to carry thecurrent Ids from the source of the transistor T₁ may then be subject tomajor ohmic drops and differ significantly in function of the positionof the transistor in the matrix.

The problem is raised to find a new matrix microelectronic device,especially for the detection of electromagnetic radiation, for exampleX-rays, whose elementary cells or pixels are respectively equipped witha current source, that does not have the disadvantages mentioned above.

DESCRIPTION OF THE INVENTION

The invention relates to a matrix microelectronic device comprising:

-   -   a plurality of elementary cells laid out according to a matrix,        respectively comprising at least one current source formed by at        least one current source transistor,    -   a source electrode of said transistor is connected to a source        biasing conductor line among a plurality of source biasing        conductor lines,    -   a gate electrode of said transistor is connected to a gate        biasing conductor line among a plurality of conductor gate        biasing lines,

wherein the device is further equipped with means for biasing conductorgate biasing lines comprising:

-   -   at least one first connection line that may be connected to one        or several of said conductor gate biasing lines,    -   means for generating, current or voltage, positioned on at least        one end of said first connection line, and designed to generate        a change or evolution or variation, for example a decrease, in        the potentials along said first connection line.

The gate biasing lines are provided to connect the respective gateelectrodes of the current respective generator transistors of the cellsof a row of cells of the matrix.

The source biasing lines are provided to connect the respective sourceselectrodes of the respective current generator transistors of the cellsof a row of cells of the matrix.

The consumption of the current source transistors especially depends ona difference between the gate potential and the source potential ofthese transistors. This invention thus provides for the use of means tocompensate an ohmic drop in one or several lines carrying the sourcepotential of the current transistors by creating a correspondingdecrease of the gate potentials, in order to obtain a difference inpotentials between gate and source, that is constant from one currentsource transistor to another. The generating means are provided so thatthe change or variation of potentials along said first connection line,is able to compensate the decrease in source potentials in one orseveral source biasing line(s).

According to a first possible embodiment, the generating means areconstantly connected to the first connection line and are in the form ofvoltage generating means comprising means for applying a first potentialvg₁ to a first end of said first connection line and means for applyinga second potential vg₂ to a second end of said first connection line,opposite the first end.

The first potential vg₁ and the second potential vg₂, may be provided infunction of at least an estimation of a diminution in potential betweenthe ends of at least one source biasing line.

This estimation may be made experimentally or using a computerisedsimulation tool.

According to a second possible embodiment, the generating means aremeans for generating a reference current, one or several rows of thematrix further comprising: at least one additional transistor fitted soas to form current mirrors, respectively with the current generatortransistors of the cells of said row of the matrix, wherein thereference current serves as the input current to said current mirrors.

According to this second possible embodiment, said first connection lineis connected to a gate biasing conductor line, when the cells connectedto this gate biasing conductor line are selected and supply their outputsignal.

The source biasing lines may be connected to one another by means of asecond connection line, wherein the additional transistors arepositioned along an additional conductor line connected to said secondconnection line.

The additional conductor line, may be identical to the source conductorbiasing lines.

According to one possibility, one or several rows of the matrix mayfurther comprise: switching means controlled by a cell row selectionsignal, capable of transmitting, in function of the state of saidselection signal, said reference current to the input of the currentmirrors of a row. The switching means may be in the form of at least oneswitching transistor.

According to one possible embodiment, the current gain of the currentmirrors may be equal to 1/K (where K>1), wherein the additionalconductor line has a linear resistance equal to or around 1/K the linearresistance of the source biasing lines. This permits the impedance to bereduced below which the gate potentials are supplied.

Said first connection line may be provided with a linear resistance thatis identical or substantially equal to the respective linear resistanceof said source biasing lines.

The transistors of a succession of current source transistors mayrespectively have a source electrode connected to a same source biasingconductor line, and a gate electrode respectively connected to one ofsaid conductor gate biasing lines.

The generating means and said first connection line may be provided toposition the gate electrode potentials of said gate electrodes of saidsuccession of transistors, to different decreasing potentials.

BRIEF DESCRIPTION OF THE DRAWINGS

This invention will be more clearly understood upon reading thedescription of embodiments provided, purely by way of example and in noway restrictively, in reference to the appended drawings among which:

FIG. 1 illustrates a matrix microelectronic device of the prior art;

FIG. 2 illustrates a first example of a matrix microelectronic device ofthe invention;

FIG. 3 illustrates a second example of matrix microelectronic device ofthe invention.

Identical, similar or equivalent parts in the various figures have thesame numerical references in order to facilitate changing from onefigure to another.

The various parts shown in the drawings are not necessarily according toa uniform scale, in order to make the figures easier to read.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

An example of a matrix microelectronic device according to theinvention, will now be provided. This device comprises a matrix of nhorizontal rows and m vertical rows of elementary cells 100 ₁₁, 100 ₁₂,. . . , 100 ₂₁, 100 ₂₂, . . . , 100 _(ij), 100 _(mn), where n may beequal to m, and for example between 1 and 10000, for example equal to2000.

The elementary cells may be for example electromagnetic radiation sensorpixels and may respectively comprise at least one electromagneticradiation detector element, for example an X-ray detector, as well as atleast one electronic circuit associated to the detector.

According to one variant, the elementary cells may be for example thecells of a reading matrix, wherein the cells are respectively associatedto a photoconductive element, for example of the CdTe, CdZnTe, PbI₂,HgI₂, PbO, Se types, hybridised or assembled or deposited onto thematrix.

The invention may apply to other types of large matrix microelectronicdevices, especially to pixel matrices respectively equipped with acurrent source.

The matrix of elementary cells may be large in size, for example aroundten square centimeters or several hundreds of square centimeters, forexample a dimension of around 10 cm×10 cm or 20 cm×20 cm.

In the case of a matrix of X-ray detectors, the elementary cells mayrespectively comprise a photo detector sensitive to visible light forexample in the form of a photodiode, or a phototransistor, coupled toone or several CsI, or Gd₂O₂S based flashing layers for example, whichpermit the X photons to be detected and which transform them intovisible photons. Components, for example made using CMOS technology,carry out the detection by transforming the visible photons intoelectrical charges.

In FIG. 2, an embodiment is shown where n=2 and m=2 elementary cells orpixels 100 ₁₁, 100 ₁₂, 100 ₂₁, 100 ₂₂.

Each elementary cell or pixel of the matrix device may comprise forexample a photodiode, as well as a plurality of transistors (thephotodiode and the transistors of each pixel are shown diagrammaticallyin the form of a block with reference 101 in FIG. 2). The device alsocomprises one or several addressing circuits and in particular at leastone addressing circuit 102 for horizontal lines or rows of the matrix,formed for example by one or several offset registers. According to onepossible embodiment of the device, the sizes detected by the pixels andtranslated in the form of signals, may be read line by line, using aselection signal Phi_line(i) of a row i (where 1≦i≦n) generated by theaddressing circuit 102.

Data lines (not shown in this figure) are provided to carry the signalsfrom the cells or pixels of a vertical row or column of the matrix,wherein these signals are then multiplexed.

One or several transistors of each pixel may be connected to a biasingline supplying a power supply potential Vdd.

Each cell or pixel of the matrix also comprises a current source, whichmay be in the form of a transistor T₁, biased so that it is insaturation operation.

Conductor lines 105 ₁, 105 ₂, for example vertical, are provided toserve as the biasing line of the respective sources of the transistorsT₁ of each pixel of a row, for example vertical, of the matrix. Thesource biasing conductor lines 105 ₁, 105 ₂ may be connected to oneanother at the edge of the matrix, by means of a connection zone 106.The source biasing lines 105 ₁, 105 ₂, respectively have a linearresistance noted R_pix(i,j). Along the source biasing lines 105 ₁, 105₂, the potential of the source electrodes of the transistors T₁ islikely to decrease.

The connection zone 106 may be in the form of at least one conductorline perpendicular to the source biasing lines 105 ₁, 105 ₂, set to apotential Vs for example of around 0 V, and provided so that it issufficiently conductive for the differences in potential at the pointsof interconnection between the conductive lines 105 ₁, 105 ₂, and theconnection 106 to be negligible, for example at least below 1 mV.

According to one possibility, to render the connection zone 106sufficiently conductive with respect to the conductor lines 105 ₁, 105₂, or to permit the connection zone 106 to transport a larger currentthan the conductor lines 105 ₁, 105 ₂, the connection zone 106 may bemade larger, for example ten or several tens of times larger than theconductor lines 105 ₁, 105 ₂. The connection zone 106 may be providedfor example, with a width of around 100 μm whilst the conductor lines105 ₁, 105 ₂ are provided with a width of around 2 μm.

The connection zone 106 may also be used on more metallicinterconnection levels than the conductor lines 105 ₁, 105 ₂. Forexample, the connection zone 106 may be used on 2 interconnection levelsusing CMOS technology, whilst the conductor lines 105 ₁, 105 ₂ may beused on a single level.

The connection zone may comprise connector pins spaced out regularlyalong a conductor line.

Conductor lines 107 ₁, 107 ₂, for example horizontal, are provided toserve as biasing lines for the respective gates of the current sourcetransistors T₁ of each pixel of a row, for example horizontal, of thematrix.

These conductor lines 107 ₁, 107 ₂ may be connected to one another, bymeans of a connection zone 108. The connection zone 108 may be in theform of at least one second conductor line, orthogonal to the gatebiasing lines 107 ₁, 107 ₂. The connection zone 108 may have a linearresistance R_lat(i) provided so that the relationshipR_lat(i)/R_pix(i,j) is constant. The conductor lines 105 ₁, 105 ₂ andthe conductor line 108 may be designed so that the relationshipR_lat(i)/R_pix(i,j) is equal to 1. In this case, the connection zone 108may be in the form of a conductor line, identical to the conductor lines105 ₁, 105 ₂.

The conductor line 108 has one end set to a first potential Vg₁, usinggenerating means comprising means 110 permitting the first potential Vg₁to be supplied and another end set to a second potential, for exampleleft free or connected to means 120 permitting a second potential Vg₂ tobe supplied that is different from the first potential. The secondpotential Vg₂ may be applied using said generating means featuring means120 permitting the second potential Vg₂ to be supplied. According to oneexample, when Vs is around 0 V, and Rlat is around 1Ω, a pixel currentof around 0.1 mA and a number of lines of around 2000, the potentialsVg₂ and Vg₁ may be around 0.7 Volts and 0.5 Volts.

By applying different Vg₁ and Vg₂ potentials to the ends of theconductor line 108, a current is forced into this conductor line 108that is connected to the gate of the current source transistors T₁. Achange in potential or a variation of potential or a decrease ofpotential is created, along the conductor line 108, so as to obtain adifferent potential at the intersection of each gate conductor line 107₁, 107 ₂ with the second conductor line.

On the device of FIG. 2, the potential at a point P₁₀, at theintersection of the first connection zone 108 and a gate biasing line107 ₁, is different from the potential at a point P₂₀, at theintersection of the first connection zone 108 and another gate biasingline 107 ₂.

The potential along each gate conductor line 107 ₁, 107 ₂ issubstantially the same along its entire length, given that the gatevoltage of the current source transistors T₁, induces very littleconsumption. For example, the potential at a point P₁₀, at theintersection of the first connection zone 108 and a gate biasing line107 ₁, is substantially equal to the potential at a second point P₁₁ ofthe gate biasing line 107 ₁, situated at the gate of a current sourcetransistor T₁, and substantially equal to the potential at a third pointP₁₂ of the gate biasing line 107 ₁, situated at the gate of anothercurrent source transistor T₁.

Two potentials Vg₂ and Vg₁, may be provided in function of an estimationof the drop in potential between the respective ends of the sourcebiasing lines 105 ₁, 105 ₂.

This estimation may be made experimentally or for example by computersimulation using software such as Pspice (Cadence) or Eldo (MentorGraphics).

For example, the two potentials Vg₂ and Vg₁, may be set so that thedifference Vg₂−Vg₁ between the two potentials, is equal to an estimationof Vs(N)−Vs(1) where 1 and N designate the pixels at the ends of avertical row of the matrix.

In this way, an ohmic drop in the lines 105 ₁, 105 ₂, carrying thesource potential to a vertical row of pixels of the matrix may becompensated by generating a change or decrease in potentialcorresponding to a conductor line perpendicular to the lines carryingthe gate potential. It is thus possible to obtain a difference betweenthe gate potential and source potential Vg−Vs that is substantiallyequal for all of the current source transistors T₁. It is thus possibleto obtain a consumption that is substantially constant from one pixel toanother of the matrix.

A second example of a device according to the invention is illustratedin FIG. 3.

This device differs from that previously described, especially in thatit comprises a conductor line reference 208 (as the conductor line 108has been removed), that is connected to the first connection zone 106connecting the source biasing conductor lines 105 ₁, 105 ₂. Theconductor line 208 is preferably identical to the source conductor lines105 ₁, 105 ₂, especially in terms of linear resistance, and may beparallel to the latter.

The device is also equipped with means 210 forming a current source I₁,for example with the aid of a transistor biased so that it has saturatedoperation, for example a PMOS transistor with a gate set to a potentialVref and a drain to a potential Vdd. The current source 210 may beplaced at the end of a conductor line 218. The current I₁ may besupplied to the respective gates of the current source transistors T₁ ofthe pixels of the matrix when these transistors are selected and theythen supply an output signal and supply current.

For this purpose, switching transistors T′₂ may be provided. Theswitching transistors T′₂ may be controlled by the selection signalphi_line of a horizontal line or row of pixels of the matrix. Theswitching transistors T′₂ may be equipped for example with a gateelectrode connected to an addressing circuit output supplying thephi_line line selection signal, wherein a source electrode is connectedto the output of the means 210 of generating the current I₁, and a drainelectrode connected to a line of gate 107 ₁ or 107 ₂. The device may beprovided so that it comprises a switching transistor T′₂ per horizontalline or row, that can connect the current source 210 to a gate conductorline 107 ₁, 107 ₂ of this line or row of the matrix selected.

Each row of the matrix may also comprise an additional transistor T′₁mounted in diode, whose source electrode is connected to the conductorline 208 and whose gate electrodes and drain are connected to oneanother and to a gate biasing line among the gate biasing lines 107 ₁,107 ₂.

The transistor T′₁ of a horizontal row or line of the matrix is fittedso that it forms a current mirror set-up with each of the currentgenerator transistors T₁ of this horizontal row or line of the matrix.

The operation of such a device may be as follows:

When a line i of the matrix is selected, the current I₁ generated by thecurrent generating means 210, passes through the switching transistorT′₂ that is made conductive by the activation of the phi_line lineselection signal. This current I₁ is evacuated by the conductor line 208to the potential Vs.

The current mirrors of a line are respectively formed by a transistorT′₁ mounted in, and a current source transistor T₁.

The conductor line 208 may be identical or substantially identical tothe source biasing lines 105 ₁, 105 ₂, especially in terms of linearresistance, and the current mirrors used so that the current I₁ is equalto the currents supplied by the pixels, wherein the source potential ofthe transistor T′₁ mounted in diode is established at the same value asthe respective source potentials of the current source transistors T₁ ofthis same line.

According to another possibility, the current generating means 210 I₁may be provided so that there is a relationship equal to K between theinput current I₁ of the current mirror and the output current of thecurrent mirror, supplied by the current source transistor T₁ of thepixels.

In this case, the gain of the current mirrors formed by the transistorT′₁ and T₁ is preferably also provided equal to 1/K, whilst theconductor line 208 may also be provided so that it has a linearresistance K times smaller than that of the source biasing conductorlines 105 ₁, 105 ₂. This may permit a reduction of the impedance belowwhich the gate voltages are supplied. To obtain current mirrors withsuch gains, the dimensions W and L, channel width and channel length ofthe transistors may be adapted, so that the current I₁ is K timesgreater than the current issued from the current source transistors T₁.

In the two embodiments that have been described above, a conductor lineis used at the edge of the matrix, that may be connected to the gatebiasing lines, and in which a evolution in voltage is created that maybe identical or proportional to that in the source biasing lines of thematrix.

The ohmic drop phenomena in the source lines are thus compensated and aconstant difference is maintained in the different pixels, between thesource potential and the gate potential of the current sourcetransistor.

The invention claimed is:
 1. Matrix microelectronic device comprising: a plurality of elementary cells laid out according to a matrix, each elementary cell of said plurality of elementary cells comprising at least one current source formed by at least one current source transistor, a source electrode of said current source transistor being connected to a source biasing conductor line, wherein the matrix microelectronic device comprises a plurality of source biasing conductor lines each connecting source electrodes of current source transistors of a respective given row of cells of the matrix, a gate electrode of said current source transistor being connected to a gate biasing conductor line, wherein the matrix microelectronic device comprises a plurality of gate biasing conductor lines each connecting gate electrodes of current source transistors of a respective different row of cells of the matrix that is orthogonal to said given row, wherein the matrix microelectronic device further comprises: a biasing device for biasing the gate biasing conductor lines, said biasing device comprising: at least one first connection line that is connected to at least several of said gate biasing conductor lines, and a voltage generator comprising a first device for applying a first potential to a first end of said first connection line and a second device for applying a second potential to a second end of said first connection line, opposite the first end, wherein said first connection line is provided with a linear resistance that is identical or substantially equal to or proportional to a respective linear resistance of said source biasing conductor lines and said voltage generator causes a decrease of potentials along said first connection line thereby compensating a corresponding decrease of potentials along the source biasing conductor lines.
 2. Matrix microelectronic device according to claim 1, the first potential and the second potential being provided in function of at least one estimation of a diminution in potential between the ends of at least one source biasing conductor line.
 3. Matrix microelectronic device according to claim 1, wherein a succession of current source transistors each have a source electrode connected to a same source biasing conductor line and a gate electrode connected to one of the gate biasing conductor lines, wherein said voltage generator and said first connection line are provided to set potentials of said gate electrodes of said succession of current source transistors to decreasing potentials.
 4. Matrix microelectronic device according to claim 1, further comprising a connection zone connecting together said source biasing conductor lines.
 5. Matrix microelectronic device comprising: a plurality of elementary cells laid out according to a matrix, each elementary cell of said plurality of elementary cells comprising at least one current source formed by at least one current source transistor, a source electrode of said current source transistor being connected to a source biasing conductor line, wherein the matrix microelectronic device comprises a plurality of source biasing conductor lines each connecting source electrodes of current source transistors of a respective given row of cells of the matrix, a gate electrode of said current source transistor being connected to a gate biasing conductor line, wherein the matrix microelectronic device comprises a plurality of gate biasing conductor lines each connecting gate electrodes of current source transistors of a respective different row of cells of the matrix that is orthogonal to said given row, wherein the matrix microelectronic device further comprises: a biasing device for biasing the gate biasing conductor lines, said biasing device comprising: at least one first connection line that is connected to at least several of said gate biasing conductor lines wherein said first connection line is provided with a linear resistance that is identical or substantially equal or proportional to a respective linear resistance of said source biasing conductor lines, and a current generator that generates a current flow through the first connection line that causes a decrease of potentials along said first connection line thereby compensating a corresponding decrease of potentials along the source biasing conductor lines.
 6. Matrix microelectronic device according to claim 5, wherein one or several rows of cells of the matrix further comprise: at least one additional transistor fitted so as to form current mirrors, respectively with the current source transistors of the cells of said row of the matrix, said current generator generating a reference current, the reference current being an input current to said current mirrors.
 7. Matrix microelectronic device according to claim 6, further comprising a connection zone connecting together said source biasing conductor lines and said first connection line.
 8. Matrix microelectronic device according to claim 7, the at least one additional transistor being positioned along said first connection line connected to said connection zone.
 9. Matrix microelectronic device according to claim 8, said first connection line being identical to the source biasing conductor lines.
 10. Matrix microelectronic device according to claim 8, a current gain of the current mirrors being equal to 1/K (where K>1), wherein the first connection line has a linear resistance K times smaller than that of the source biasing conductor lines.
 11. Matrix microelectronic device according to claim 6, wherein one or several rows of cells of the matrix further comprise: switching means controlled by a selection signal for selecting a row of cells of the matrix, that can transmit, in function of a state of said selection signal, said reference current to an input of the current mirrors of a row of cells of the matrix. 